TLE6285 Datasheet, PDF (8/23 Pages) Infineon Technologies AG – LIN-Transceiver LDO

Target Data TLE 6285
very short, the V_LD level is not reached and no reset-signal is asserted. This feature
avoids resets at short negative spikes at the output voltage e.g. caused by load changes.
As soon as the output voltage is more positive than the reset threshold, the delay
capacitor is charged with constant current. When the voltage reaches V_UD the reset
output RO is set High again.
The reset threshold is either the internal defined V_RT voltage (typical 4.6 V) or can be
lowered by a voltage level at the R_Th input down to 3.5 V. The reset delay time and the
reset reaction time are defined by the external capacitor C_D. The reset function is active
down to V_I = 1 V.
The device is capable to supply 150 mA. For protection at high input voltage above 25 V,
the output current is reduced (SOA protection).
2.5 Reset
The power on reset feature is necessary for a defined start of the microprocessor when
switching on the application. For the reset delay time after the output voltage of the
regulator is above the reset threshold, the reset signal is set High again. The reset delay
time is defined by the reset delay capacitor C_D at pin RD (refer to figure 4 and 5).
The under-voltage reset circuitry supervises the output voltage. In case V_Q decreases
below the reset threshold the reset output is set LOW after the reset reaction time. The
reset LOW signal is generated down to an output voltage V_CC to 1 V. Both the reset
reaction time and the reset delay time is defined by the capacitor value.
The power on reset delay time is defined by the charging time of an external delay
capacitor C_D.
C_D = (t_d ´ I_D) / DV
[1]
With
C_D reset delay capacitor
t_d reset delay time
DV = V_UD,
typical 1.8 V for power up reset
DV = V_UD – V_LD typical 1.35 V for undervoltage reset
I_D charge current typical 6.5 mA
For a delay capacitor C_D =100 nF the typical power on reset delay time is 28 ms.
The reset reaction time t_RR is the time it takes the voltage regulator to set reset output
LOW after the output voltage has dropped below the reset threshold. It is typically 1 ms
for delay capacitor of 100 nF. For other values for C_D the reaction time can be estimated
using the following equation:
t_RR = 10 ns / nF ´ C_D
[2]
The reset output is an open collector output with a pull-up resistor of typical 20 kW to Q.
An external pull-up can be added with a resistor value of at least 5.6 kW.
Version 1.02
8
2002-05-15