TLE6236G Datasheet, PDF (8/15 Pages) Infineon Technologies AG – Smart Octal Low-Side Switch

Datasheet TLE 6236 G
Power Transistor Protection Functions¹⁾
Each of the eight output stages has its own zener clamp, which causes a voltage limitation at
the power transistor when solenoid loads are switched off. The outputs are provided with a
current limitation set to a minimum of 500 mA. The continuous current for each channel is
200 mA (all channels ON).
Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and a fault bit is generated for each output indi-
vidually (early warning). If this operation leads to an overtemperature condition, a second
protection level (about 170 °C) will change the output into a low duty cycle PWM (channel se-
lective thermal shutdown with restart) to prevent critical chip temperatures.
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6236 G by means of the CS
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS High to Low transition: - diagnostic status information is transferred from the
power
outputs into the shift register.
- serial input data can be clocked in from then on
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits
CS Low to High transition: - transfer of SI bits from shift register into output buffers
- reset of diagnosis register
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of CS . When CS is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
The device will react to the CS only if one correct SCLK signal has been sent.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE 6236 G.
The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while
the serial output (SO) shifts diagnostic information out of the shift register on the rising edge of
serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select CS
makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-
mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
A logic high bit at this pin (within the data byte) will switch the corresponding output on.
1)_{The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or perma-}
nently
V2.1
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26.Aug. 2002