TLE4942-1C Datasheet, PDF (8/31 Pages) Infineon Technologies AG – Differential Two-Wire Hall Effect Sensor-IC

TLE4942-1C
Circuit Description
The circuit is supplied internally by a voltage regulator. An on-chip oscillator serves as a
clock generator for the DSP and the output encoder.
Speed Signal Circuitry
TLE4942-1C speed signal path comprises of a pair of Hall Effect probes, separated from
each other by 2.5 mm, a differential amplifier including noise limiting low-pass filter, and
a comparator triggering a switched current output stage. An offset cancellation feedback
loop is provided through a signal-tracking A/D converter, a digital signal processor
(DSP), and an offset cancellation D/A converter.
During the power-up phase the output is disabled (low state).
Uncalibrated Mode
Occasionally a short initial offset settling time t_d,input might delay the detection of the input
signal (the sensor is “blind”). This happens at power on or when a stop pulse is issued.
The magnetic input signal is tracked by the speed ADC and monitored within the digital
circuit. For detection of a magnetic edge the signal transient needs to exceed a threshold
(digital
noise
constant,
Δ
Bˆ
Limit,
early
startup^).
Only
the
first
edge
is
suppressed
internally.
With
the second detected edge pulses are issued at the output. When the signal slope is
identified as a rising edge (or falling edge), a comparator is triggered. The comparator is
triggered again as soon as a falling edge (or rising edge respectively) is detected (and
vice versa). The minimum and maximum values of the input signal are extracted and
their corresponding arithmetic mean value is calculated. The offset of this mean value is
determined and fed into the offset cancellation DAC.
Between the startup of the magnetic input signal and the time when its second extreme
is reached, the PGA (programmable gain amplifier) will switch to its appropriate position.
This value is determined by the signal amplitude and initial offset value. The digital noise
constant value is increased, leading to a change in phase shift between magnetic input
signal and output signal. After that consecutive output pulses should have a nominal
delay of about 180°.
Transition to Calibrated Mode
In the calibrated mode the phase shift between input and output signal is no longer
determined by the ratio between digital noise constant and signal amplitude. Therefore
a sudden change in the phase shift may occur during the transition from uncalibrated to
calibrated mode.
Calibrated Mode
During the uncalibrated mode the offset value is calculated by the peak detection
algorithm. In running mode (calibrated mode) the offset correction algorithm of the DSP
Data Sheet
9
V 4. 0, February 2010