TLD5095EL Datasheet, PDF (8/31 Pages) Infineon Technologies AG – DC/DC Boost, Buck-Boost, SEPIC controller

TLD5095EL
General Product Characteristics
Absolute Maximum Ratings¹⁾
T_j = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Min.
Max.
4.1.26 ESD Resistivity to GND
V_ESD,CDM
-500
500
V
4.1.27 ESD Resistivity Pin 1, 7, 8, 14 (corner V_ESD,CDM,C -750
750
V
pins) to GND
1) Not subject to production test, specified by design.
2) ESD susceptibility, Human Body Model “HBM” according to EIA/JESD 22-A114B
3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1
Conditions
CDM³⁾
CDM³⁾
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Functional Range
Pos. Parameter
4.2.1
4.2.2
Supply Voltage Input
Feedback Voltage Input
4.2.3 Junction Temperature
Symbol
V_IN
V_FBH;
V_FBL
T_j
Limit Values
Min.
Max.
4.75
45
4.5
45
-40
150
Unit Conditions
V
V_IVCC > V_IVCC,RTH,d
V
–
°C –
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
4.3.1
4.3.2
4.3.3
4.3.4
Junction to Case ^{1) 2)}
Junction to Ambient^{1) 3)}
R_thJC
–
R_thJA
–
R_thJA
–
R_thJA
–
–
10
K/W
47
–
K/W 2s2p
54
–
K/W 1s0p + 600 mm²
64
–
K/W 1s0p + 300 mm²
1) Not subject to production test, specified by design.
2) Specified R_thJC value is simulated at natural convection on a cold plate setup (all pins and exposed pad are fixed to ambient
temperature). Ta=25°C, IC is dissipating 1W.
3) Specified R_thJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink
area at natural convection on FR4 board; The device was simulated on a 76.2 x 114.3 x 1.5mm board. The 2s2p board has
2 outer copper layers (2 x 70µm Cu) and 2 inner copper layers (2 x 35µm Cu), A thermal via (diameter = 0.3mm and 25µm
plating) array was applied under the exposed pad and connected the first outer layer (top) to the first inner layer and second
outer layer (bottom) of the JEDEC PCB. Ta=25°C, IC is dissipating 1W.
Datasheet
8
Rev. 1.1, 2009-12-16