SLE66CX320P Datasheet, PDF (8/9 Pages) Infineon Technologies AG – Security & Chip Card ICs

SLE 66CX320P
General Description
SLE 66CX320P is the first product of Infineon Technologies high end security controller family in
advanced 0.25 µm CMOS technology. The CPU provides the high efficiency of the SAB 8051
instruction set extended by additional powerful instructions together with enhanced performance,
memory sizes and security features. The internal clock frequency can be adjusted up to 15 MHz
independent of the clock rate of the terminal with the help of the PLL.
The controller IC offers 63 Kbyte of User-ROM, 256 bytes internal RAM, 2048 bytes XRAM and 32
Kbytes EEPROM. The Memory Management Unit allows a secure separation of the operating
system and the applications. Furthermore the MMU makes a secure downloading of applications
possible after the personalization of a card. These new features suit the requirements of the next
generation of multi application operating systems. For code compatibility to the SLE 66CxxS
family, a transparent mode for the MMU is established which allows to keep the memory mapping
of the SLE 66CxxS products.
Voltage
Clock
Reset
ROM
XRAM EEPROM DES-EC2
Advanced
64 Kbyte 2 Kbyte 32 Kbyte Accelerator Crypto Engine
16-Bit CPU with
MMU
&
ECO 2000
Instruction Set
Address-/Data Bus
Sleep Mode Logic
Sensors/Filters
Voltage Regulator
Interrupt
two
16-bit
Timers
CRC
Random
Number
Generator
UART
PLL
Figure 2 Block Diagram SLE 66CX320P
The CRC module allows the easy generation of checksums according to ISO 3309 (16-Bit-CRC).
To minimize the overall power consumption, the chip card controller IC offers a sleep mode. The
UART supports the half-duplex transmission protocols T=0 and T=1 according to ISO 7816-3. All
relevant transmission parameters can be adjusted by software, as e.g. the clock division factor,
direct/inverse convention and the number of stop bits. Additionally, the I/O port can be driven by
communication routines realized in software.
The Advanced Crypto Engine is equipped with its own RAM of 700 bytes and supports all of today
known public-key algorithms based on large integer modular arithmetic. It allows fast and efficient
calculation of e.g. RSA operations with key lengths up to 2048 bit.
The DDES-EC2 accelerator consists of two modules. The DES module supports symmetrical
crypto algorithms according to the Data Encryption Standard in the Electronic Code Book Mode.
The EC2 module accelerates the multiplication in GF(2ⁿ) and therefore the operations for elliptic
curve cryptography.
The random number generator (RNG) is able to supply the CPU with true random numbers on all
conditions.
As an important measure, the chip provides a new and enhanced level of on-chip security features.
Preliminary Short Product Information
8/9
08.01