SLE88CFX4002P Datasheet, PDF (7/10 Pages) Infineon Technologies AG – Security & Chip Card ICs

SLE 88CFX4002P
Block Diagram
Sensor/Filter:
Voltage
Clock
Reset
Temperature
Scalable
CLK
UART
EEPROM
400 Kbyte
Code/Data
RAM
16 KByte
ROM
240 Kbyte
32-bit Bus
32-bit CPU
with
Memory
Management
and Protection
Unit
Figure 2:
Voltage
Regulator
16-bit
Timers
Crypto@1408Bit
880 Byte RAM
DES
Accelerator
Random
Number
Generator
SLE 88CFX4002P, 32-bit CPU and Peripherals
General Description
SLE 88CFX4002P is the most sophisticated smart card microcontroller on the market. It is
manufactured in 0.13 micron CMOS technology and only differs from SLE 88CFX4000P in its
additional 160 Kbytes User ROM. In this product family, Infineon Technologies realises increased
security and performance while reducing power consumption, and additionally provides a platform
for real multi-application and multi-tasking operating systems.
Performance and Virtual Machine Acceleration
Performance is first of all enhanced by the 32-bit architecture that processes instructions and data
32-bit wise. This is supported by the implementation of cache memories in the core that allow
faster access to instructions and data. Performance is also enhanced by a clock frequency of up to
66MHz. And finally, efficient support and an additional performance increase of multi-application
schemes are gained by a hardware acceleration of Virtual Machine Languages like Java Card ^TM or
MULTOS^TM.
Large Memories
The 32-bit architecture allows the linear addressing of large memories for a more convenient code
implementation. With the 0.13 micron process, SLE 88CFX4002P offers largest on-chip-memories
with 240 Kbytes of ROM (160 Kbytes User ROM and 80 Kbytes reserved ROM), 400 Kbytes of
EEPROM, and 16 Kbytes of RAM. The separate ROM is reserved for the Platform Support Layer
(PSL) and the Self Test Software (STS) that are provided by Infineon Technologies, so that these
lower code layers do not occupy the user memory space. The large EEPROM space is the basis of
Infineon Technologies “Flash” Concept where the entire EEPROM is configurable in code and data
sections with 4Kbytes granularity, and so it can be used to store Operating System program code
and data, as well as application code and data. Each application can be tailored to fit its targeted
project. This customization provides added value to the system and the possibility to serve multiple
projects with the same platform. The 400K EEPROM are e.g. configurable as 256 Kbytes of code
and 144 Kbytes of data or 320 Kbytes of code and 80 Kbytes of data. This concept offers the
flexibility and convenience of Flash memory, but takes advantage of the EEPROM cell quality
(timing, cycling and endurance).
Preliminary Short Product Information 7 / 10
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