IPG16N10S4L-61A Datasheet, PDF (7/9 Pages) Infineon Technologies AG – Dual N-channel Logic Level - Enhancement mode

IPG16N10S4L-61A
13 Avalanche energy⁵⁾
E _AS = f(T _j), I _D = 8A
14 Drain-source breakdown voltage
V _BR(DSS) = f(T _j); I _D = 1 mA
40
110
108
30
106
104
20
102
100
10
98
96
0
25
50
75 100 125 150 175
T_j [°C]
94
-60 -20 20 60 100 140 180
T_j [°C]
15 Typ. gate charge⁵⁾
V _GS = f(Q _gate); I _D = 16 A pulsed
parameter: V _DD
16 Gate charge waveforms
12
V _GS
20 V
Q_g
10
8
80 V
6
V _{g s(th)}
4
2
Q _{g (th)}
0
0
2
4
6
8
10
Q_gate [nC]
Q _gs
Rev. 1.0
page 7
Q _sw
Q _gd
Q _gate
2014-06-30