C165 Datasheet, PDF (64/77 Pages) Siemens Semiconductor Group – C16x-Family of High-Performance CMOS 16-Bit Microcontrollers

C165
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2t_A + t_C + t_F (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol Max. CPU Clock Variable CPU Clock Unit
= 20 MHz
1 / 2TCL = 1 to 20 MHz
min. max.
min.
max.
Data float after RdCS
(with RW-delay)¹⁾
t₅₃ SR –
30 + t_F –
2TCL - 20 ns
+ 2t_A + t_F
1)
Data float after RdCS
(no RW-delay)¹⁾
t₆₈ SR –
5 + t_F
–
TCL - 20 ns
+ 2t_A + t_F
1)
Address hold after
t₅₅ CC - 16 + t_F –
- 16 + t_F –
ns
RdCS, WrCS
Data hold after WrCS t₅₇ CC 9 + t_F –
TCL - 16 –
ns
+ t_F
1) _{RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).}
2) _{Read data are latched with the same clock edge that triggers the address change and the rising RD edge.}
Therefore address changes before the end of RD have no impact on read cycles.
3) _{These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are}
specified together with the address and signal BHE (see figures below).
Data Sheet
60
V2.0, 2000-12