XC87XCLM_11 Datasheet, PDF (61/145 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller

XC87xCLM
Functional Description
3.2.4.11 UART1 Registers
The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 15 UART1 Register Overview
Addr Register Name
Bit
7
6
5
RMAP = 1
C8_H
SCON
Reset: 00_H Bit Field
Serial Channel Control Register
Type
C9_H
SBUF
Reset: 00_H Bit Field
Serial Data Buffer Register
Type
CA_H
BCON
Reset: 00_H Bit Field
Baud Rate Control Register
Type
CB_H
BG
Reset: 00_H
Baud Rate Timer/Reload
Register
Bit Field
Type
CC_H
FDCON
Reset: 00_H
Fractional Divider Control
Register
Bit Field
Type
CD_H
FDSTEP
Reset: 00_H
Fractional Divider Reload
Register
Bit Field
Type
CE_H
FDRES
Reset: 00_H
Fractional Divider Result
Register
Bit Field
Type
CF_H
SCON1
Reset: 07_H
Serial Channel Control Register
1
Bit Field
Type
SM0
rw
SM1
rw
SM2
rw
0
r
0
r
0
r
4
3
2
1
0
REN TB8 RB8
TI
RI
rw
rw
rwh
rwh
rwh
VAL
rwh
BRPRE
R
rw
rw
BR_VALUE
rwh
NDOV
rwh
FDM
rw
FDEN
rw
STEP
rw
RESULT
rh
NDOV
EN
rw
TIEN
rw
RIEN
rw
3.2.4.12 SSC Registers
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 16 SSC Register Overview
Addr Register Name
Bit
7
RMAP = 0
A9_H SSC_PISEL
Reset: 00_H Bit Field
Port Input Select Register
Type
AA_H SSC_CONL
Reset: 00_H Bit Field LB
Control Register Low
Programming Mode
Type
rw
AA_H
SSC_CONL
Reset: 00_H
Control Register Low
Operating Mode
Bit Field
Type
AB_H SSC_CONH
Reset: 00_H Bit Field EN
Control Register High
Programming Mode
Type
rw
6
5
4
3
2
1
0
0
r
PO
PH
rw
rw
0
r
MS
0
rw
r
HB
rw
AREN
rw
BEN
rw
CIS
SIS
rw
rw
BM
rw
BC
rh
PEN
rw
REN
rw
MIS
rw
TEN
rw
Data Sheet
54
V1.5, 2011-03