PEB20570 Datasheet, PDF (60/291 Pages) Infineon Technologies AG – ICs for Communications

DELIC
Interface Description
FSC
DCL
F-bit
Ch0 bit0
Ch1 bit0 (data)
Ch2 bit0
125 µs
3.072 MHz
data ctrl
LT-S mode:
U_PN mode:
data
DX/DR
Ch7 bit0 (data)
Ch0 bit1
Ch1 bit0 (ctrl)
Ch2 bit1
Ch7 bit0 (ctrl)
Ch1,3,5,7 in S mode (LT-S)
Ch0,2,4,6 in U_PN mode
Ch0 bit2
Ch1 bit1 (data)
Ch2 bit2
Ch7 bit1 (data)
last bit of U_PN frame
last bit of LT-S frame
Ch6 bit37
Ch7 bit 23 (ctrl)
Figure 3-2 IOM-2000 Data Sequence (1 VIP with 8 Channels)
Note: 1. Data transfer on IOM-2000 interface always starts with the MSB (related to B
channels), whereas CMD and STAT bits transfer always starts with LSB (bit 0)
of any register
2. All registers follow the Intel structure (LSB=2⁰, MSB=2³¹)
3. Unused bits are don’t care (’x’)
4. The order of reception or transmission of each VIP channel is always
channel 0 to channel 7. A freely programmable channel assignment of multiple
VIPs on IOM-2000 (e.g., ch0 of VIP_0, ch1 of VIP_0, ch0 of VIP_1, ch2 of
VIP_0, ...) is not possible.
Preliminary Data Sheet
3-4
2003-08