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TLE42764 Datasheet, PDF (6/17 Pages) Infineon Technologies AG – Low Dropout Linear Voltage Regulator
TLE42764
General Product Characteristics
Pos.
Parameter
Symbol
Limit Values Unit Remarks
Min.
Max.
4.2.4 Output Capacitor’s
CQ
22
–
4.2.5
Requirements for Stability
ESR(CQ) –
3
µF 1)
Ω
2)
4.2.6 Junction temperature
Tj
-40
150
°C –
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
2) relevant ESR value at f = 10 kHz
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
TLE42764GV (PG-TO263-5)
4.3.1 Junction to Case1)
RthJC
–
3.6
–
K/W measured to heat
slug
4.3.2
4.3.3
Junction to Ambient1)
RthJA
–
–
22
–
74
–
K/W
K/W
2)
footprint only3)
4.3.4
–
42
–
K/W 300 mm² heatsink
area3)
4.3.5
–
34
–
K/W 600 mm² heatsink
area3)
TLE42764DV (PG-TO252-5)
4.3.6 Junction to Case1)
RthJC
–
3.6
–
K/W measured to heat
slug
4.3.7
4.3.8
Junction to Ambient1)
RthJA
–
–
27
–
115 –
K/W
K/W
2)
footprint only3)
4.3.9
–
52
–
K/W 300 mm² heatsink
area3)
4.3.10
–
40
–
K/W 600 mm² heatsink
area3)
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
6
Rev. 1.1, 2009-10-09