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TLE6368_06 Datasheet, PDF (56/59 Pages) Infineon Technologies AG – Multi-Voltage Processor Power Supply
TLE 6368 / SONIC
5.8 Layout recommendation
The most sensitive points for Buck converters - when considering the layout - are the
nodes at the input and the output of the Buck switch, the DMOS transistor.
For proper operation the external catch diode and Buck inductance have to be
connected as close as possible to the SW pins (29, 31). Best suitable for the connection
of the cathode of the Schottky diode and one terminal of the inductance would be a small
plain located next to the SW pins.
The GND connection of the catch diode must be also as short as possible. In general the
GND level should be implemented as surface area over the whole PCB as second layer,
if necessary as third layer.
The pin FB/L_IN is sensitive to noise. With an appropriate layout the Buck output
capacitor helps to avoid noise coupling to this pin. Also filtering of steep edges at the
supply voltage pin e.g. as shown in the application diagram is mandatory. CI2 may either
be a low ESR Tantalum capacitor or a ceramic capacitor. A minimum capacitance of
10µF is recommended for CI2.
To obtain the optimum filter capability of the input π-filter it has to be located also as
close as possible to the IN pins, at least the ceramic capacitor CI3 should be next to those
pins.
Data Sheet
56
Rev. 2.2, 2006-12-01