XMC1100AB Datasheet, PDF (53/68 Pages) Infineon Technologies AG – Microcontroller Series for Industrial Applications

XMC^™1100 AB-Step
XMC^™1000 Family
Electrical Parameter
3.3.5 SPD Timing Requirements
The optimum SPD decision time between 0_B and 1_B is 0.75 µs. With this value the
system has maximum robustness against frequency deviations of the sampling clock on
tool and on device side. However it is not always possible to exactly match this value
with the given constraints for the sample clock. For instance for a oversampling rate of
4, the sample clock will be 8 MHz and in this case the closest possible effective decision
time is 5.5 clock cycles (0.69 µs).
Table 26 Optimum Number of Sample Clocks for SPD
Sample Sampling Sample Sample Effective Remark
Freq.
Factor
Clocks 0_B Clocks 1_B Decision
Time¹⁾
8 MHz 4
1 to 5
6 to 12
0.69 µs
The other closest option
(0.81 µs) for the effective
decision time is less robust.
1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0_B sample clocks)
For a balanced distribution of the timing robustness of SPD between tool and device, the
timing requirements for the tool are:
• Frequency deviation of the sample clock is +/- 5%
• Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal
sample frequency)
Data Sheet
53
V1.7, 2016-08
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