TLE4473GV53_08 Datasheet, PDF (5/16 Pages) Infineon Technologies AG – Dual Low Drop Voltage Regulator Output 2: 180 mA, 5 V (±2%)

TLE 4473 GV53
TLE 4473 GV52
P-DSO-12-6
WI
1
RO2
2
RO1
3
Q2
4
Q1
5
N.C.
6
12
GND
11
D1
10
D2
9
INH2
8
INH1
7
I
Figure 3
AEP03318_4473gv53.VSD
Pin 6 and heat slug should be connected to GND
Pin Configuration TLE 4473 GV53, TLE 4473 GV52 (top view)
Table 1
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
Heatsink
Pin Definitions and Functions (TLE 4473 GV53, TLE 4473 GV52)
Symbol Function
WI
Watchdog input; input for watchdog pulses, positive edge
triggered
RO2 Reset output for Q2; open collector output
RO1 Reset and watchdog output for Q1; open collector output
Q2
Q1
N.C.
Output voltage 2 (5 V); block to GND with a capacitor C_Q2 ≥ 22 µF,
ESR < 5 Ω at 10 kHz or C_Q2 ≥ 10 µF, ESR < 4 Ω at 10 kHz
Output voltage 1 (3.3 V/2.6 V); block to GND with a capacitor
C_Q1 ≥ 10 µF, ESR < 5 Ω at 10 kHz
Not connected; connect to GND
I
Input voltage; block to GND directly at the IC with a ceramic
capacitor.
INH1 Inhibit input 1; low level at INH2 and INH1 disables Q2 and Q1
INH2 Inhibit input 2; low level disables Q2
D2
Reset Delay 2; connect a capacitor to set reset delay for Q2
D1
Reset Delay 1; connect a capacitor to GND to set reset delay and
watchdog timing for Q1
GND Ground
N. C. Not connected; connect to GND
Data Sheet
5
Rev. 1.1, 2008-09-19