TLE4473GV52 Datasheet, PDF (5/15 Pages) Infineon Technologies AG – Dual Low Drop Voltage Regulator

TLE 4473 GV53
TLE 4473 GV52
P-DSO-12-6
WI
1
RO2
2
RO1
3
Q2
4
Q1
5
N.C.
6
12
GND
11
D1
10
D2
9
INH2
8
INH1
7
I
Figure 3
AEP03318_4473gv53.VSD
Pin 6 and heat slug should be connected to GND
Pin Configuration TLE 4473 GV53, TLE 4473 GV52 (top view)
Table 1
Pin Definitions and Functions (TLE 4473 GV53, TLE 4473 GV52)
Pin No. Symbol Function
1
WI
Watchdog input; input for watchdog pulses, positive edge
triggered
2
RO2 Reset output for Q2; open collector output
3
RO1 Reset and watchdog output for Q1; open collector output
4
Q2
Output voltage 2 (5 V); block to GND with a capacitor C_Q2 ≥ 22 µF,
ESR < 5 Ω at 10 kHz or C_Q2 ≥ 10 µF, ESR < 4 Ω at 10 kHz
5
Q1
Output voltage 1 (3.3 V/2.6 V); block to GND with a capacitor
C_Q1 ≥ 10 µF, ESR < 5 Ω at 10 kHz
6
N.C. Not connected; connect to GND
7
I
Input voltage; block to GND directly at the IC with a ceramic
capacitor.
8
INH1 Inhibit input 1; low level at INH2 and INH1 disables Q2 and Q1
9
INH2 Inhibit input 2; low level disables Q2
10
D2
Reset Delay 2; connect a capacitor to set reset delay for Q2
11
D1
Reset Delay 1; connect a capacitor to GND to set reset delay and
watchdog timing for Q1
12
GND
Heatsink N. C.
Ground
Not connected; connect to GND
Data Sheet
5
Rev. 1.0, 2004-07-14