TLE7270-2 Datasheet, PDF (4/20 Pages) Infineon Technologies AG – 5-V Low Dropout Voltage Regulator

3
Pin Configuration
3.1
Pin Assignment PG-SSOP-14 Exposed Pad
QF

52


QF

,
QF


QF
*1'


QF
QF


QF
'7


4
QF


QF
7/(B3,1&21),*B6623
69*
TLE7270-2
Pin Configuration
Figure 2 Pin Configuration (top view)
3.2
Pin Definitions and Functions PG-SSOP-14 Exposed Pad
Pin No.
1,3,5,7
2
4
6
8,10,11,12,14
9
13
Pad
Symbol Function
n.c.
non connected
can be open or connected to GND
RO
Reset Output
open collector output with integrated pull-up resistor;
optional external pull-up resistor of ≥ 10 kΩ to pin Q;
leave open if reset function not needed
GND Ground
DT
Delay Timing
connect to GND or Q to choose the Power On Reset Delay Time
n.c.
non connected
can be open or connected to GND
Q
Output
block to ground with a capacitor close to the IC terminals, respecting the values given
for its capacitance and ESR in “Functional Range” on Page 6
I
Input
block to ground directly at the IC with a ceramic capacitor
–
Exposed Pad
connect to GND and heatsink area
Data Sheet
4
Rev. 1.01, 2009-07-23