AUIRLR014N Datasheet, PDF (4/10 Pages) International Rectifier – Advanced Planar Technology Logic-Level Gate Drive

500
400 C_iss
V_GS = 0V, f = 1MHz
C_iss = C_gs + C_{gd ,} C_ds SHORTED
C_rss = C_gd
C_oss = C_ds + C_gd
300
C_oss
200
C_rss
100
0
1
10
100
V_DS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
AUIRLR014N
15 _{ID = 6 A}
10
V_DS = 44V
V_DS = 27V
5
FOR TEST CIRCUIT
0
SEE FIGURE 13
0
2
4
6
8
10
Q_G, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
100
10
T_J = 175° C
1
0.1
0.2
T_J = 25 ° C
V _GS = 0 V
0.6
1.0
1.4
1.8
V_SD,Source-to-Drain Voltage (V)
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
4
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R_DS(on)
10us
100us
1ms
1
10ms
T_C
T_J
=
=
25° C
175° C
Single Pulse
0.1
1
10
100
V_DS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
2015-12-11