BTS5590G Datasheet, PDF (38/46 Pages) Infineon Technologies AG – SPI Power Controller

SPOC - BTS5590G
Serial Peripheral Interface (SPI)
10.2
Daisy Chain Capability
The SPI of SPOC - BTS5590G provides daisy chain capability. In this configuration several devices are activated
by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see
Figure 23), in order to build a chain. The ends of the chain are connected with the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the
SCLK line of each device in the chain.
device 1
device 2
device 3
SI
SO SI
SO SI
SO
MO
SPI
SPI
SPI
MI
MCS
MCLK
Figure 23 Daisy Chain Configuration
SPI_DasyChain.emf
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out occures at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished.
In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy
chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in
daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high
(see Figure 24).
MI
MO
MCS
MCLK
time
SO device 3
SI device 3
SO device 2
SI device 2
Figure 24 Data Transfer in Daisy Chain Configuration
SO device 1
SI device 1
SPI_DasyChain2.emf
10.3
Timing Diagrams
CS
t_CS(lead)
SCLK
SI
t_SO(en)
SO
t_SCLK(P)
t_SCLK(H) t_SCLK(L)
t_SI(su)
t_SI(h)
t_SO(v)
Figure 25 Timing Diagram SPI Access
t_CS(lag)
t_CS(td)
0.7Vdd
0.2V_dd
0.7V_dd
0.2V_dd
0.7V_dd
0.2Vdd
t_{SO( d is)}
0.7V_dd
0.2V_dd
SPI Timing.emf
Data Sheet
38
Rev. 1.3, 2007-10-30