TDA21320 Datasheet, PDF (35/36 Pages) Infineon Technologies AG – Desktop and Server Vcore and non-Vcore buck-converter

TDA21320
Board Layout Recommendations
11
Board Layout Recommendations
The PCB (printed circuit board) layout design follows the listed industry standards:
- Recommended vias: 10 mil⁸ hole with 20 mil via pad diameter, 12 mil hole with 24 mil via pad diameter
- Minimum (typical) via to via center distance: 25 mil (30 … 35 mil)
- Minimum feature width: 5 mil
- Minimum (typical) clearance: 5 mil (15 … 20 mil)
Commonly, 10 mil via drill diameters are used for PCBs up to 150 mil thicknesses (usually 22 layers). For thicker
boards, 12 mil vias are recommended. To reduce voltage spikes caused by parasitic circuit inductance, all primary
decoupling capacitors for VIN, VDRV, BOOT and VCIN should be of MLCC type, X6S or X7R rated and located at
the same board side as the powerstage close to their respective pins. This is especially important for the VIN to
PGND MLCCs.
Electrical and thermal connection of the powerstage to the PCB is crucial for achieving high efficiency. Therefore,
vias in VIN and PGND pads are required in the pad areas to connect most effectively to other power and PGND
layers. Bigger value MLCC input capacitors should be placed at the bottom side of the PCB close to the vias of the
powerstage’s VIN and PGND pads. To reduce the stray inductance in the current commutation loop it is strongly
recommended to have the 2^nd layers from the top and the bottom of the board to be monolithic ground planes. All
logic and signal connections between powerstage and controller should be embedded between two ground layers.
The routing of the current sense lines back to the controller has to be done differentially, for example with 5 mil
spacing and 10 – 15 mil distances to other potentials. If the PCB features more than 10 layers, the passive
components associated with the current sense lines should be located only at the top side of the board. All resistors
and capacitors near the powerstage should be in 0402 case size. For minimizing distribution loss to the load and
maintaining signal integrity, have multiple layers/planes in parallel and ensure that the copper cross section for
PGND is at least as big as it is for Vout.
Figure 22 Generic Board Design
8 _{Unit conversion: 1 mil = 25.4 μm}
Data Sheet
35
Revision 2.4, 2015-07-16