XC866_05 Datasheet, PDF (344/396 Pages) Infineon Technologies AG – 8-Bit Single Chip Microcontroller

XC866
13.4.8.1 Event Interrupts
event 7
event 6
event 5
event 4
CHINF4
interrupt
trigger 0
rh
AND
IEN
rw
EVINP4
rw
Analog-to-Digital Converter
to SR0
to SR0
to SR0 to SR1
to SR0 _{to SR1}
to SR1
to SR1
event 1
event 0
interrupt
trigger 0
CHINF0
rh
AND
ENSI
rw
EVINP0
rw
to SR0
to SR0
to SR1
to SR1
Figure 13-13 Event Interrupt Structure
Event interrupts can be generated by the request sources and the result registers. The
event interrupt enable bits are located in the request sources (ENSI) and result register
control (IEN). An interrupt node pointer (EVINP) for each event allows the selection of
the targeted service output line.
A request source event is generated when the requested channel conversion is
completed:
• Event 0: Request source event of sequential request source 0 (arbitration slot 0)
• Event 1: Request source event of parallel request source 1 (arbitration slot 1)
A result event is generated according to the data reduction control (see
Section 13.4.7.3):
• Event 4: Result register event of result register 0
• Event 5: Result register event of result register 1
• Event 6: Result register event of result register 2
• Event 7: Result register event of result register 3
User’s Manual
ADC, V 0.3
13-22
V 0.2, 2005-01