PEB2256 Datasheet, PDF (334/490 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

10.2
FALC56 V1.2
PEB 2256
T1/J1 Registers
Detailed Description of T1/J1 Control Registers
Transmit FIFO - HDLC Channel 1 (Write)
7
XFIFO
XFIFO
XF7
XF15
0
XF0
(00)
XF8
(01)
Writing data to XFIFO of HDLC channel 1 can be done in 8-bit (byte) or 16-bit (word)
access. The LSB is transmitted first.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO following an XPR
interrupt.
Command Register (Write)
Value after reset: 00_H
7
0
CMDR RMC RRES XREP XRES XHF XTF XME SRES (02)
RMC
RRES
XREP
Receive Message Complete - HDLC Channel 1
Confirmation from CPU to FALC56 that the current frame or data
block has been fetched following an RPF or RME interrupt, thus the
occupied space in the RFIFO can be released. If RMC is given while
RFIFO is already cleared, the next incoming data block is cleared
instantly, although interrupts are generated.
Receiver Reset
The receive line interface except the clock and data recovery unit
(DPLL), the receive framer, the one-second timer and the receive
signaling controller are reset. However the contents of the control
registers is not deleted.
Transmission Repeat - HDLC Channel 1
If XREP is set together with XTF (write 24H to CMDR), the FALC56
repeatedly transmits the contents of the XFIFO (1 to 32 bytes) without
HDLC framing fully transparently, i.e. without flag, CRC.
The cyclic transmission is stopped with an SRES command or by
resetting XREP.
Data Sheet
334
2002-08-27