TDA5255E1 Datasheet, PDF (33/93 Pages) Infineon Technologies AG – ASK/FSK 434MHz Wireless Transceiver

TDA5255 E1
Version 1.1
Confidential
Functional Description
Note: It is required to activate the device for the duration of t_SYSSU after first power on or a reset.
Only if this is done the normal operation timing is performed.
With default settings the clock generating units are disabled during PD, therefore no clock is
available at the clock output pin. It is possible to offer a clock signal at the clock output pin every
time (also during PD) if the CLK_EN Bit in the CONFIG register is set to HIGH.
STATUS
XTAL EN
DC OFFSET COMPENSATION
PEAK DETECTOR EN
DATADETECTION EN
POWER AMP EN
t_CLKSU
0.5ms
RESET
or 1^st POWER ON
PWDDD = low
TX activ or RX activ
PD
CLOCK FOR EXTERNAL µP
if RX
if RX
if RX
t_TXSU
1.1ms
t_SYSSU
8ms
if TX
t_CLKSU
0.5ms
t_RXSU
2.2ms
t_DDSU
2.6ms
Figure 2-15 1^st start or reset in active mode
Note: The time values are typical values
TX activ
PD
t_TXSU
1.1ms
t_CLKSU
0.5ms
RX activ
TX activ
RX activ
t_RXSU
2.2ms
t_DDSU
2.6ms
t_TXSU
1.1ms
t_RXSU
2.2ms
t_DDSU
2.6ms
Sequenzer_Timing_pupstart.wmf
STATUS
XTAL EN
DC OFFSET COMPENSATION
PEAK DETECTOR EN
DATADETECTION EN
POWER AMP EN
RESET
or 1^st POWER ON
PWDDD = high
PD
CLOCK FOR EXTERNAL µP
t_CLKSU
0.5ms
PWDDD = low
TX activ or RX activ
PD
t_TXSU
1.1ms
t_SYSSU
8ms
if RX
if RX
if RX
if TX
t_CLKSU
0.5ms
t_RXSU
2.2ms
t_DDSU
2.6ms
Figure 2-16 1st start or reset in PD mode
TX activ
RX activ
t_TXSU
1.1ms
t_RXSU
2.2ms
t_DDSU
2.6ms
Sequenzer_Timing_pdstart.wmf
Preliminary Specification
33
2002-11-28