XC800 Datasheet, PDF (31/132 Pages) Infineon Technologies AG – Microcontroller Family Architecture and Instruction Set

XC800
CPU Architecture
2.1.11 Interrupt Registers
Each interrupt for a peripheral (if available for the derivative) can be individually enabled
or disabled by setting or clearing the corresponding bit in the bitaddressable interrupt
enable registers IEN0 and IEN1. Register IEN0 also contains the global enable/disable
bit (EA), which can be cleared to disable all interrupts at once. The Non-Maskable
Interrupt (NMI) is always enabled.
After reset, the enable bits of IEN0 and IEN1 are cleared to 0. This implies that the
corresponding interrupts are disabled.
IEN0
Interrupt Enable Register 0
Reset Value: 00_H
7
6
5
4
3
2
1
0
EA
0
ET2
ES
ET1
EX1
ET0
EX0
rw
r
rw
rw
rw
rw
rw
rw
Field
EX0
ET0
EX1
ET1
ES
ET2
Bits Type Description
0
rw Enable External Interrupt 0
0 External Interrupt 0 is disabled.
1 External Interrupt 0 is enabled.
1
rw Enable Timer 0 Overflow Interrupt
0 Timer 0 Overflow interrupt is disabled.
1 Timer 0 Overflow interrupt is enabled.
2
rw Enable External Interrupt 1
0 External interrupt 1 is disabled.
1 External interrupt 1 is enabled.
3
rw Enable Timer 1 Overflow Interrupt
0 Timer 1 Overflow interrupt is disabled.
1 Timer 1 Overflow interrupt is enabled.
4
rw Enable Serial Port Interrupt
0 Serial Port interrupt is disabled.
1 Serial Port interrupt is enabled.
5
rw Enable Timer 2 Interrupt
0 Timer 2 interrupt is disabled.
1 Timer 2 interrupt is enabled.
User’s Manual, V 0.1
2-14
2005-01