IPG20N10S4L-35A Datasheet, PDF (3/9 Pages) Infineon Technologies AG – Dual N-channel Logic Level - Enhancement mode

IPG20N10S4L-35A
Parameter
Dynamic characteristics²⁾
Input capacitance⁴⁾
Output capacitance⁴⁾
Reverse transfer capacitance⁴⁾
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate Charge Characteristics^{2, 4)}
Gate to source charge
Gate to drain charge
Gate charge total
Gate plateau voltage
Reverse Diode
Diode continous forward current²⁾
one channel active
Diode pulse current²⁾
one channel active
Diode forward voltage
Reverse recovery time²⁾
Symbol
Conditions
min.
Values
typ.
Unit
max.
C _iss
-
C _oss
V _GS=0 V, V _DS=25 V,
f =1 MHz
-
C_rss
-
t _d(on)
-
t_r
V _DD=50 V, V _GS=10 V,
-
t _d(off)
I _D=20 A, R _G=11 Ω
-
t_f
-
850 1105 pF
285
370
30
60
3
- ns
2
-
18
-
13
-
Q _gs
Q _gd
V _DD=80 V, I _D=20 A,
Q_g
V _GS=0 to 10 V
V _plateau
-
2.9
3.8 nC
-
3.2
6.4
-
13.4 17.4
-
3.5
-V
I_S
I _S,pulse
T _C=25 °C
V _SD
V _GS=0 V, I _F=17 A,
T _j=25 °C
t _rr
V _R=50 V, I _F=I _S,
di _F/dt =100 A/µs
-
-
20 A
-
-
80
-
1.0
1.3 V
-
50
- ns
Reverse recovery charge^{2, 4)}
Q _rr
-
75
- nC
1) _{Current is limited by bondwire; with an R thJC = 3.5K/W the chip is able to carry 24A at 25°C.}
2) _{Specified by design. Not subject to production test.}
3) _{Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm}2 _{(one layer, 70 µm thick) copper area for drain}
connection. PCB is vertical in still air.
4) _{Per channel}
Rev. 1.0
page 3
2013-03-04