IPD50N06S4L-08 Datasheet, PDF (3/9 Pages) Infineon Technologies AG – OptiMOS-T2 Power-Transistor

IPD50N06S4L-08
Parameter
Dynamic characteristics²⁾
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate Charge Characteristics²⁾
Gate to source charge
Gate to drain charge
Gate charge total
Gate plateau voltage
Reverse Diode
Diode continous forward current²⁾
Diode pulse current²⁾
Diode forward voltage
Reverse recovery time²⁾
Symbol
Conditions
C _iss
C _oss
C_rss
t _d(on)
t_r
t _d(off)
t_f
V _GS=0V, V _DS=25V,
f =1MHz
V _DD=30V, V _GS=10V,
I _D=50A, R _G=3.5Ω
Q _gs
Q _gd
V _DD=48V, I _D=50A,
Q_g
V _GS=0 to 10V
V _plateau
I_S
I _S,pulse
T _C=25°C
V _SD
V _GS=0V, I _F=50A,
T _j=25°C
t _rr
V _R=30V, I _F=I _S,
di _F/dt =100A/µs
min.
Values
typ.
Unit
max.
-
3680 4780 pF
-
840 1090
-
40
80
-
9
- ns
-
2
-
-
45
-
-
8
-
-
13
19 nC
-
5
10
-
49
64
-
3.6
-V
-
-
50 A
-
-
200
0.6
0.95
1.3 V
-
33
- ns
Reverse recovery charge²⁾
Q _rr
-
32
- nC
1) _{Current is limited by bondwire; with an R thJC = 2.1K/W the chip is able to carry 65A at 25°C.}
2) _{Specified by design. Not subject to production test.}
3) _{Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm}2 _{(one layer, 70 µm thick) copper area for drain}
connection. PCB is vertical in still air.
Rev. 1.0
page 3
2009-03-24