IPD50N03S4L-06 Datasheet, PDF (3/9 Pages) Infineon Technologies AG – OptiMOS-T2 Power-Transistor

Parameter
IPD50N03S4L-06
Symbol
Conditions
min.
Values
typ.
Unit
max.
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
C _iss
C _oss
C_rss
V _GS=0V, V _DS=25V,
f =1MHz
-
1790 2330 pF
-
460
600
-
17
34
t _d(on)
-
3
- ns
t_r
V _DD=15V, V _GS=10V,
-
1
-
t _d(off)
I _D=30A, R _G=1.6Ω
-
19
-
t_f
-
7
-
Gate Charge Characteristics²⁾
Gate to source charge
Gate to drain charge
Gate charge total
Gate plateau voltage
Q _gs
Q _gd
V _DD=24V, I _D=50A,
Q_g
V _GS=0 to 10V
V _plateau
-
6
8 nC
-
3
6
-
24
31
-
3.2
-V
Reverse Diode
Diode continous forward current²⁾
Diode pulse current²⁾
Diode forward voltage
Reverse recovery time²⁾
I_S
I _S,pulse
V _SD
T _C=25°C
V _GS=0V, I _F=50A,
T _j=25°C
t _rr
V _R=30V, I _F=I _S,
di _F/dt =100A/µs
-
-
50 A
-
-
200
0.6
0.95
1.3 V
-
17
- ns
Reverse recovery charge²⁾
Q _rr
-
14
- nC
1) _{Current is limited by bondwire; with an R thJC = 2.7K/W the chip is able to carry 77A at 25°C.}
2) _{Defined by design. Not subject to production test.}
3) _{Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm}2 _{(one layer, 70 µm thick) copper area for drain}
connection. PCB is vertical in still air.
Rev. 1.0
page 3
2008-08-05