TLE4678-2_15 Datasheet, PDF (24/33 Pages) Infineon Technologies AG – Low Drop Out Linear Voltage Regulator

TLE4678-2
Watchdog Function
V_WI
VWI,hi
tWI,p
V_WI
VWI,hi
1 / fWI
VWI,lo
d VWI / d t
VWI,lo
t
t
Figure 9 Test Pulses Watchdog Input WI
Watchdog Timing
Positive edges at the watchdog input pin “WI” are expected within the watchdog trigger time frame t_WI,tr, otherwise
a low signal at pin “WO” is generated. If a watchdog low signal at pin “WO” is generated, it remains low for t_WD,lo.
All watchdog timings are defined by charging and discharging the capacitor C_D at pin “D”. Thus, the watchdog
timing can be programmed by selecting C_D. For timing details see also Figure 10.
In case a watchdog trigger time period t_WI,tr different from the value for C_D = 100nF is required, the delay
capacitor’s value can be derived from the specified value given in Table “Watchdog Trigger Time” on Page 26:
C_D = 100nF × t_WI,tr / t_WI,tr,100nF
(5)
The watchdog output low time t_WD,lo and the watchdog period t_WD,p then becomes:
t_WD,lo = t_WD,lo,100nF × C_D / 100nF
(6)
t_WD,p = t_WI,tr + t_WD,lo
(7)
The formula is valid for C_D ≥ 10nF. For precise timing calculations consider also the delay capacitor’s tolerance.
V_WI
V _{W I,h i}
V _{W I,lo}
V_D
V_DW,hi
V_DW,lo
V_WO
No positive
V_WI edge
dV_WI/ dt
outside spec
1/ f_WI
t _{W I,p}
t
t_WI,tr
T_WI,p
t
t _{W D ,lo}
t _{W D ,lo}
V _{W O,low}
Figure 10 Timing Diagram Watchdog
Data Sheet
24
T i mi n g Di a g ra m_ W a t ch d o g .vsd
t
Rev. 1.0, 2014-03-03