PEF3452 Datasheet, PDF (23/71 Pages) Infineon Technologies AG – Line Interface Unit for DS3, STS 1 and E3

PEF 3452
TE3-LIU V1.3
PRELIMINARY
Pin Descriptions
Table 2
Control Pin Functions (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
Supply (S)
43
JATT
I + PD
Jitter Attenuation Enable
This signal has to be stable during reset
and may not change afterwards. It must not
be connected to a µP bus.
0 = no jitter attenuation (default if left open)
1 = jitter attenuation in transmit direction
22
LOS
O
Loss of Signal Indication
0 = correct signal
1 = loss of signal
LOS is synchronized on RCLK. During
LOS, a clock signal is generated internally
and driven on RCLK.
1) _{If RL=LL=1, the device is set into power down mode.}
Preliminary Data Sheet
13
2001-12-05