IPP13N03LBG Datasheet, PDF (2/9 Pages) Infineon Technologies AG – OptiMOS®2 Power-Transistor

Parameter
Symbol Conditions
Thermal characteristics
Thermal resistance, junction - case
SMD version, device on PCB
R _thJC
R _thJA
minimal footprint
6 cm² cooling area⁵⁾
IPP13N03LB G
min.
Values
typ.
Unit
max.
-
-
2.9 K/W
-
-
62
-
-
40
Electrical characteristics, at T _j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
Gate threshold voltage
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
Gate resistance
Transconductance
V _(BR)DSS V _GS=0 V, I _D=1 mA
30
V _GS(th) V _DS=V _GS, I _D=20 µA
1.2
I _DSS
V _DS=30 V, V _GS=0 V,
T _j=25 °C
-
V _DS=30 V, V _GS=0 V,
T _j=125 °C
-
I _GSS
V _GS=20 V, V _DS=0 V
-
R _DS(on) V _GS=4.5 V, I _D=20 A
-
V _GS=10 V, I _D=30 A
-
R_G
-
g _fs
|V _DS|>2|I _D|R _DS(on)max,
I _D=60 A
-
-V
1.6
2
0.1
1 µA
10
100
1
100 nA
15.2 18.9 mΩ
10.7 12.8
1
-Ω
57
-S
2) _{Current is limited by bondwire; with an R thJC=2.9 K/W the chip is able to carry 47 A.}
3) _{See figure 3}
4) _{T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V}
5) _{Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm}2 _{(one layer, 70 µm thick) copper area for drain}
connection. PCB is vertical in still air.
5 _{Diagrams are related to straight lead versions.}
Rev. 0.93
page 2
2006-05-10