IPC302N12N3 Datasheet, PDF (2/4 Pages) Infineon Technologies AG – N-channel enhancement mode

OptiMOS™3PowerMOSTransistorChip
IPC302N12N3
1Description
•N-channelenhancementmode
•FordynamiccharacterizationrefertothedatasheetofIPB038N12N3G
•AQL0.65forvisualinspectionaccordingtofailurecatalogue
•ElectrostaticDischargeSensitiveDeviceaccordingtoMIL-STD883C
•Diebond:solderedorglued
•Backsidemetallization:NiVsystem
•Frontsidemetallization:AlSisystem
•Passivation:nitride(onlyonedgestructure)
PowerMOSTransistorChip
Table1KeyPerformanceParameters
Parameter
Value
Unit
V(BR)DSS
RDS(on)
Die size
120
3.8¹⁾
6.7 x 4.5
V
mΩ
mm²
Thickness
250
µm
Drain
Gate
Source
Type/OrderingCode
IPC302N12N3
Package
Chip
Marking
not defined
RelatedLinks
-
2ElectricalCharacteristicsonWaferLevel
atTj=25°C,unlessotherwisespecified
Table2
Parameter
Drain-source breakdown voltage
Gate threshold voltage
Zero gate voltage drain current
Gate-source leakage current
Drain-source on- resistance
Reverse diode forward on-voltage
Avalanche energy, single pulse
Symbol
V(BR)DSS
VGS(th)
IDSS
IGSS
RDS(on)
VSD
EAS
Min.
120
2
-
-
-
-
-
Values
Typ. Max.
-
-
3
4
0.1 1
1
100
2.5²⁾ 100³⁾
1.0 1.2
45⁴⁾ -
Unit Note/TestCondition
V VGS=0V,ID=1mA
V
VDS=VGS,ID=275µA
µA VGS=0V,VDS=100V
nA VGS=20V,VDS=0V
mΩ VGS=10V,ID=2.0A
V
VGS=0V,IF=1A
mJ ID =30 A, RGS =25 Ω
1) _{packaged in a P-TO263-3 (see ref. product)}
2)_{typicalbaredieRDS(on);VGS=10V}
3) _{limited by wafer test-equipment}
4) _{Wafer tested. For general avalanche capability refer to the datasheet of IPB038N12N3 G}
Final Data Sheet
2
Rev.2.5,2014-07-25