IPC045N10L3 Datasheet, PDF (2/4 Pages) Infineon Technologies AG – N-channel enhancement mode

OptiMOS™3PowerMOSTransistorChip
IPC045N10L3
1Description
•N-channelenhancementmode
•FordynamiccharacterizationrefertothedatasheetofBSZ150N10LS3G
•AQL0.65forvisualinspectionaccordingtofailurecatalogue
•ElectrostaticDischargeSensitiveDeviceaccordingtoMIL-STD883C
•Diebond:solderedorglued
•Backsidemetallization:NiVsystem
•Frontsidemetallization:AlCusystem
•Passivation:nitride(onlyonedgestructure)
PowerMOSTransistorChip
Table1KeyPerformanceParameters
Parameter
Value
Unit
V(BR)DSS
RDS(on)
Die size
100
15¹⁾
2.5 x 1.8
V
mΩ
mm²
Thickness
220
µm
Drain
Gate
Source
Type/OrderingCode
IPC045N10L3
Package
Chip
Marking
not defined
RelatedLinks
-
2ElectricalCharacteristicsonWaferLevel
atTj=25°C,unlessotherwisespecified
Table2
Parameter
Drain-source breakdown voltage
Gate threshold voltage
Zero gate voltage drain current
Gate-source leakage current
Drain-source on- resistance
Reverse diode forward on-voltage
Avalanche energy, single pulse
Symbol
V(BR)DSS
VGS(th)
IDSS
IGSS
RDS(on)
VSD
EAS
Min.
100
1.1
-
-
-
-
-
Values
Typ. Max.
-
-
1.7 2.1
0.01 1
1
100
16²⁾ 100³⁾
0.9 1.2
80⁴⁾ -
Unit Note/TestCondition
V VGS=0V,ID=1mA
V
VDS=VGS,ID=33µA
µA VGS=0V,VDS=100V
nA VGS=20V,VDS=0V
mΩ VGS=4.5V,ID=2.0A
V VGS=0V,IF=1A
mJ ID =20 A, RGS =25 Ω
1) _{packaged in a PG-TDSON-8 (see ref. product). Maximum RDS(on) at VGS=10V}
2)_{typicalbaredieRDS(on);VGS=4.5V}
3) _{limited by wafer test-equipment}
4) _{Wafer tested. For general avalanche capability refer to the datasheet of BSZ150N10LS3 G}
Final Data Sheet
2
Rev.2.5,2014-07-09