TLE9262-3QXV33 Datasheet, PDF (194/197 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9262-3QXV33
Application Information
Cross Section (JEDEC 2s2p) with Cooling Area
Cross Section (JEDEC 1s0p) with Cooling Area
70µm modelled(traces)
35µm, 90% metalization*
35µm, 90% metalization*
70µm / 5% metalization+ cooling area
*: means percentual Cu metalization on each layer
PCB (top view)
PCB (bottom view)
Detail SolderArea
Figure 68 Board Setup
Board setup is defined according to JESD 51-2,-5,-7.
Board: 76.2x114.3x1.5mm³ with 2 inner copper layers (35µm thick), with thermal via array under the exposed pad
contacting the first inner copper layer and 300mm² cooling area on the bottom layer (70µm).
Data Sheet
194
Rev. 1.1, 2014-10-23