TDA21321 Datasheet, PDF (19/32 Pages) Infineon Technologies AG – Desktop and Server Vcore and non-Vcore buck-converter

TDA21321
Theory of Operation
For example, having a permissible 500 mV voltage range at the receiver side to report positive current of 100 A,
the resistor that has to be used in the IMONREF path can be calculated as:
V_IMON  V_{IMONREF _ CM}  500mV
R_IMONREF
 ^{VIMON  VIMONREF _ CM}
I_OUT  a_CS
500mV
 _{100A  6.67 106}
 750
(6)
Having a resistor value of 348 Ω will result in the following voltage difference:
V_IMON  V_{IMONREF _CM}  R_IMONREF  I_OUT  a_CS  348 100A  6.67 10^6  232mV
(7)
The sensing of current occurs in the HS-MOSFET and the LS-MOSFET during their respective on-times. During
tri-state condition both MOSFETs are in off-state without sensing. The current reported is then zero. If the tri-
state condition was present for more than 19 µs (typ.), current reporting resumes with a delay of 1 µs (typ.).
OCP: By design of the application the current should never exceed the OCP tripping threshold I_OCPtrip. The duty
cycle is being truncated by the TDA21321 when the current exceeds I_OCPtrip. This prevents the part from being
destroyed by excessive current. A counter is being increased counting consecutive PWM duty cycle truncations.
The counter is being reset at the first non-truncated PWM duty cycle. When the counter reaches the value of 10,
a fault will be reported at TMON/FAULT by pulling it to ‘high’ level signaling the PWM controller the need for
immediate action to prevent catastrophic failure. This fault is latched and will be released when VCIN and/or
VDRV are being re-cycled.
5.4.6
Shoot Through Protection
The TDA21321 driver includes gate drive functionality to protect against shoot through. In order to protect the
power stage from overlap, both high-side and low-side MOSFETs being on at the same time, the adaptive
control circuitry monitors specific voltages. When the PWM signal transitions to low, the high-side MOSFET will
begin to turn-off after the propagation delay time t_pdlu. When V_GS of the high-side MOSFET is discharged
below 1 V (a threshold below which the high-side MOSFET is off), a secondary delay t_pdhl is initiated. After
that delay the low-side MOSFET turns on regardless of the state of the “PHASE” pin. It ensures that the
converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each
switching cycle. See Figure 9 for more detail.
Data Sheet
19
Revision 2.4, 2015-07-16