PMA51XX Datasheet, PDF (165/202 Pages) Infineon Technologies AG – RF Transmitter ASK/FSK 315/434/868/915 MHz, Embedded 8051 Microcontroller, 10-bit ADC

PMA51xx
Functional Description
2.17
SPI Interface
The Serial Peripheral Interface (SPI) is a very simple synchronous interface to transfer data on a serial bus,
connecting an intelligent master controller with general-purpose slave circuits such as slave controller, RAMs,
memories, and so on. A simple 2-wire (half-duplex mode) or 3-wire (full-duplex mode) bus is used for
communication.
• High-speed synchronous data transfer
• Four programmable bit rates through prescaler
• 2-wire bus for half-duplex transmission; a serial clock line (SPI_Clk) and concatenated data line
(SPI_MISO,SPI_MOSI)
• 3-wire bus for full-duplex transmission; a serial clock line (SPI_Clk) and two serial data lines
(SPI_MISO,SPI_MOSI)
• A 4-wire bus for full-duplex transmission plus handshaking can be implemented by also utilizing the Chip
Select (SPI_CS). This pin can be used for indicating the beginning of a new byte sequence.
• Master or Slave Operation
• Clock Control - Polarity (idle low/high) and phase (sample data with rising/falling clock edge) are
programmable
• Bit Width (1 to 8 bits) and Bit Order (MSB or LSB first) are configurable
• Compatible with SSC (High-Speed Synchronous Serial Interface) and standard SPI interfaces
• Protocol is defined by software
2.17.1 SPI Functionality
The basic interaction principle between master and slave SPI devices is shown in Figure 60. Writing to the SPI
shift register of the master SPI device starts the SPI clock generation (line SCK). The two 8 bit shift registers in
master and slave device can be considered as one distributed circular shift register (including line MISO and
MOSI). When data is shifted from the master to the slave with the generated clock, data is also shifted in the
opposite direction simultaneously. During one shift cycle, data in the master and the slave is interchanged resulting
a full duplex transmission.
SPI Master Device
8 bit Shift-Register
MISO
MOSI
MISO
MOSI
SPI Slave Device
MISO
MOSI
8 bit Shift-Register
SPI ClockGen
SCK
SCK
SCK
Figure 60 SPI principle
Different SPI devices are connected through three lines. The definition of these lines is always determined by the
master. The line connected to the master's data output is the transmit line MOSI¹⁾, the receive line is connected
to its data input line MISO²⁾. The serial clock is distributed over line SCK³⁾. Only the device selected for master
operation generates and outputs the serial clock. All slaves receive and react to this clock.
1) MOSI = Master Out Slave In
2) MISO = Master In Slave Out
3) SCK = Serial clock
Data Sheet
165
Revision 2.1, 2010-06-02