PEF2256H Datasheet, PDF (163/518 Pages) Infineon Technologies AG – E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications

FALC^®56
PEF 2256 H/E
Functional Description T1/J1
XL1/
XDOP/
XOID
XL2/
XDON
DR
DR
D
A
Pulse Shaper
Framer
Transmit
Elastic
XDI
Store
XCLK
TCLK
(E1: 8MHz)
(T1: 6MHz)
÷4
E1: 8MHz
T1: 6MHz
DCO-X
Transmit
Jitter
Attenuator
SCLKR
Internal Clock of
Receive System
Interface
SCLKX
TCLK
RCLK
MCLK
Clocking
Unit
Figure 56 Transmit Clock System (T1/J1)
Note: DR = Dual-Rail interface
DCO-X Digital Controlled Oscillator transmit
ITS10305
5.4.4 Transmit Elastic Buffer (T1/J1)
The transmit elastic store with a size of max. 2 × 193 bit (two frames) serves as a
temporary store for the PCM data to adapt the system clock (SCLKX) to the internally
generated clock for the transmit data, and to retranslate time slot structure used in the
system to that of the line side. Its optimal start position is initiated when programming the
transmit time slot offset values. A difference in the effective data rates of system side and
transmit side lead to an overflow or underflow of the transmit memory. Thus, errors in
data transmission to the remote end occur. This error condition (transmit slip) is reported
to the microprocessor by interrupt status registers.
The received bit stream from pin XDI is optionally stored in the transmit elastic buffer.
The memory is organized as the receive elastic buffer. Programming of the transmit
buffer size is done by SIC1.XBS1/0:
• XBS1/0 = 00: bypass of the transmit elastic buffer
• XBS1/0 = 01: one frame buffer or 193 bits
Maximum of wander amplitude (peak-to-peak): (1 UI = 648 ns)
System interface clocking rate: modulo 2.048 MHz:
User’s Manual
163
Hardware Description
DS1.1, 2003-10-23