TDA7110 Datasheet, PDF (14/39 Pages) Infineon Technologies AG – ASK/FSK Transmitter 868/433 MHz

TDA7110
Functional Description
2.4 Functional Blocks
2.4.1 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator
(VCO), an asynchronous divider chain, a phase detector, a charge pump and a
loop filter. It is fully implemented on chip. The tuning circuit of the VCO consist-
ing of spiral inductors and varactor diodes is on chip, too. Therefore no addi-
tional external components are necessary. The nominal center frequency of the
VCO is 869 MHz. The oscillator signal is fed both, to the synthesizer divider
chain and to the power amplifier. The overall division ratio of the asynchronous
divider chain is 128 in case of a 6.78 MHz crystal or 64 in case of a 13.56 MHz
crystal and can be selected via CSEL (pin 16). The phase detector is a Type IV
PD with charge pump. The passive loop filter is realized on chip.
2.4.2 Crystal Oscillator
The crystal oscillator operates either at 6.78 MHz or at 13.56 MHz.
The reference frequency can be chosen by the signal at CSEL (pin 16).
Table 2-3
CSEL (pin 16)
Low¹⁾
Open²⁾
1) Low: Voltage at pin < 0.2 V
2) Open: Pin open
Crystal Frequency
6.78 MHz
13.56 MHz
For both quartz frequency options, 847.5 kHz or 3.39 MHz are available as out-
put frequencies of the clock output CLKOUT (pin 8) to drive the clock input of a
micro controller.
The frequency at CLKOUT (pin 8) is controlled by the signal at CLKDIV (pin 9)
Table 2-4
CLKDIV (pin 9)
Low¹⁾
Open²⁾
1) Low: Voltage at pin < 0.2 V
2) Open: Pin open
CLKOUT Frequency
3.39 MHz
847.5 kHz
Wireless Components
2-8
Data Sheet, December 2008