XC886_09 Datasheet, PDF (133/144 Pages) Infineon Technologies AG – 8-Bit Single Chip Microcontroller

XC886/888CLM
Electrical Parameters
4.3.3 Power-on Reset and PLL Timing
Table 49 provides the characteristics of the power-on reset and PLL timing in the
XC886/888.
Table 46 Power-On Reset and PLL Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
min. typ. max.
Pad operating voltage
On-Chip Oscillator
start-up time
V_PAD
t_OSCST
CC 2.3 –
CC – –
–
V
1)
500 ns ¹⁾
Flash initialization time t_FINIT
CC – 160 –
µs ¹⁾
RESET hold time
t_RST
SR – 500 –
µs V_DDP rise time
(10% – 90%) ≤
500µs¹⁾²⁾
PLL lock-in in time
t_LOCK
CC –
–
200 µs ¹⁾
PLL accumulated jitter D_P
–
–
0.7 ns ¹⁾³⁾
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
2) RESET signal has to be active (low) until V_DDC has reached 90% of its maximum value (typ. 2.5 V).
3) PLL lock at 96 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 48 and P = 1.
Data Sheet
126
V1.2, 2009-07