ICE2QS03G_14 Datasheet, PDF (13/24 Pages) Infineon Technologies AG – Active burst mode for low standby power

Quasi-Resonant PWM controller
ICE2QS03G
Functional Description
Figure 7 Gate rising waveform
3.4
Current Limitation
There is a cycle by cycle current limitation realized by the current limit comparator to provide an over-current
detection. The source current of the MOSFET is sensed via a sense resistor R_CS. By means of R_CS the source
current is transformed to a sense voltage V_CS which is fed into the pin CS. If the voltage V_CS exceeds an internal
voltage limit, adjusted according to the Mains voltage, the comparator immediately turns off the gate drive.
To prevent the Current Limitation process from distortions caused by leading edge spikes, a Leading Edge
Blanking time (t_LEB) is integrated in the current sensing path.
A further comparator is implemented to detect dangerous current levels (V_CSSW) which could occur if one or
more transformer windings are shorted or if the secondary diode is shorted. To avoid an accidental latch off, a
spike blanking time of t_CSSW is integrated in the output path of the comparator.
3.4.1 Foldback Point Correction
When the main bus voltage increases, the switch on time becomes shorter and therefore the operating
frequency is also increased. As a result, for a constant primary current limit, the maximum possible output
power is increased which is beyond the converter design limit.
To avoid such a situation, the internal foldback point correction circuit varies the V_CS voltage limit according to
the bus voltage. This means the V_CS will be decreased when the bus voltage increases. To keep a constant
maximum input power of the converter, the required maximum V_CS versus various input bus voltage can be
calculated, which is shown in Figure 8.
Figure 8 Variation of the V_CS limit voltage according to the I_ZC current
Data Sheet
13
V2.3, 2014-03-06