PEB20550HV1.3 Datasheet, PDF (122/252 Pages) Infineon Technologies AG – 2 Channel Serial Optimized Communication Controller for HDLC/PPP

PEB 20525
PEF 20525
Register Description (GPISL)
Register 10
GPISL
GPP Interrupt Status Register (Low Byte)
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
read only
00_H
0A_H
written by SEROCCO-H, read and evaluated by CPU
Bit
7
6
5
4
3
2
1
0
GPP Interrupt Status Bits
0
0
0
0
0
GP10I GP9I
GP8I
Register 11
GPISH
GPP Interrupt Status Register (High Byte)
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
read only
00_H
0B_H
written by SEROCCO-H, read and evaluated by CPU
Bit
7
0
6
GP6I
5
4
3
2
GPP Interrupt Status Bits
0
0
0
GP2I
1
GP1I
0
GP0I
Data Sheet
5-122
2000-09-14