TLE6208-3G_07 Datasheet, PDF (12/22 Pages) Infineon Technologies AG – Triple Half Bridges Optimized for DC motor management applications

TLE 6208-3 G
2.3 Electrical Characteristics (cont’d)
8 V < V_S < 40 V; 4.75 V < V_CC < 5.25 V; INH = High; all outputs open; – 40 °C < T_j < 150 °C;
unless otherwise specified
Parameter
Symbol Limit Values Unit Test Condition
min. typ. max.
Note: Capacitances are guaranteed by design.
SPI-Interface
Delay Time from Stand-by to Data In/Power on Reset
Setup time
t_set
–
–
100 µs –
Logic Inputs DI, CLK and CSN
H-input voltage threshold V_IH
L-input voltage threshold
V_IL
Hysteresis of input voltage V_IHY
Pull up current at pin CSN I_ICSN
Pull down current at pin DI I_IDI
Pull down current at pin CLK I_ICLK
Input capacitance
C_I
at pin CSN, DI or CLK
–
0.52 0.7 V_CC –
0.2 0.48 –
V_CC –
50 200 500 mV –
– 50 – 25 – 10 µA
10 25 50 µA
10 25 50 µA
–
10 15 pF
V_CSN = 0.7 × V_CC
V_DI = 0.2 × V_CC
V_CLK = 0.2 × V_CC
0 V < V_CC <
5.25 V
Note: Capacitances are guaranteed by design.
Logic Output DO
H-output voltage level
V_DOH
V_CC V_CC –
– 1.0 – 0.7
V
I_DOH = 1 mA
L-output voltage level
Tri-state leakage current
V_DOL
I_DOLK
Tri-state input capacitance C_DO
–
0.2 0.4 V I_DOL = – 1.6 mA
– 10 0
10
µA V_CSN = V_CC
0 V < V_DO < V_CC
–
10 15 pF V_CSN = V_CC
0 V < V_CC <
5.25 V
Note: Capacitances are guaranteed by design.
Data Sheet
12
2007-09-12