TDA21310 Datasheet, PDF (12/23 Pages) Infineon Technologies AG – Desktop and Server buck-converter

UVLO Output
Logic Level
“H”
Shutdown
“L”
TDA21310
Theory of Operation
Enable
V_{UVLO_F}
V_{UVLO_R}
V_CIN
Figure 4 Internal Output Signal from UVLO Unit
5.2
Inputs to the Internal Control Circuits
The PWM is the control input to the IC from an external PWM controller and is compatible with 3.3 V.
The PWM input has tri-state functionality. When the voltage remains in the specified PWM-shutdown-window for
at least the PWM-shutdown-holdoff time t_tsshd, the operation will be suspended by keeping both MOSFET
gate outputs low. Once left open, the pin is held internally at a level of V_{PWM_O} = 1.5 V level.
Table 12 PWM Pin Functionality
PWM logic level
Low
High
Open (left floating, or high impedance)
Driver output
GL= High, GH = Low
GL = Low, GH = High
GL = Low, GH = Low
Using a wide range VCIN power supply (from 4.5 V to 6 V) causes a shifting in the threshold voltages for the
following parameters: V_{PMW_O}, V_{PWM_H}, V_{PWM_L}. The typical behavior of these thresholds over VCIN voltage
variation is shown in the following graph.
Data Sheet
12
Revision 2.1, 2013-09-05