TLE42994 Datasheet, PDF (11/30 Pages) Infineon Technologies AG – Low Dropout Fixed Voltage Regulator

TLE42994
General Product Characteristics
4.3
Thermal Resistance
Pos. Parameter
Symbol
Limit Value
Unit Conditions
Min. Typ. Max.
TLE42994G (PG-DSO-8)
4.3.4
4.3.5
4.3.6
Junction to Soldering Point¹⁾
Junction to Ambient¹⁾
R_thJSP
–
R_thJA
–
–
–
60 K/W measured to pin 5
113 –
K/W
2)
185 –
K/W Footprint only³⁾
4.3.7
–
142 –
K/W 300mm² heatsink area on
PCB³⁾
4.3.8
–
136 –
K/W 600mm² heatsink area on
PCB³⁾
TLE42994GM (PG-DSO-14)
4.3.9
4.3.10
4.3.11
Junction to Soldering Point¹⁾
Junction to Ambient¹⁾
R_thJSP
–
R_thJA
–
–
–
30 K/W measured to all GND pins
63 –
K/W
2)
112 –
K/W Footprint only³⁾
4.3.12
–
73 –
K/W 300mm² heatsink area on
PCB³⁾
4.3.13
–
65 –
K/W 600mm² heatsink area on
PCB³⁾
TLE42994E (PG-SSOP-14)
4.3.14
4.3.15
4.3.16
Junction to Case¹⁾
Junction to Ambient¹⁾
R_thJC
–
R_thJA
–
–
10 –
47 –
140 –
K/W
K/W
K/W
–
2)
Footprint only³⁾
4.3.17
–
63 –
K/W 300mm² heatsink area on
PCB³⁾
4.3.18
–
53 –
K/W 600mm² heatsink area on
PCB³⁾
1) not subject to production test, specified by design
2) Specified R_thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified R_thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with 1 copper layer (1 x 70µm Cu).
Data Sheet
11
Rev. 1.1, 2009-05-19