ISL78310 Datasheet, PDF (11/13 Pages) Intersil Corporation – High Performance 1A LDO

ISL78310
Equation 3 can be used to calculate C_SS for a desired in-rush
current, where V_OUT is the output voltage, C_OUT is the total
capacitance on the output, and I_INRUSH is the desired in-rush
current.
C_SS
=
(_---V_{---O----U----T---}x_---C_{----O---U----T---}x_---2_----μ_----A_----)
I _{I N R U S H} x 0.5 V
(EQ. 3)
The scopes in Figure 14 to 33 capture the response for the soft-
start function. The output voltage is set to 1.8V.
The external capacitor is always discharged to ground at the
beginning of start-up or enabling.
Power-Good Operation
The PGOOD is a logic output that indicates the status of V_OUT.
The PGOOD flag is an open-drain NMOS that can sink 10mA
during a fault condition. The PGOOD pin requires an external pull-
up resistor, which is typically connected to the VOUT pin. The
PGOOD pin should not be pulled up to a voltage source greater
than V_IN. PGOOD goes low when the output voltage drops below
84% of the nominal output voltage or if the part is disabled. The
PGOOD comparator fuctions during current limit and thermal
shutdown. For applications not using this feature, connect this
pin to ground.
Output Voltage Selection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
programmed to any level between 0.8V and 5V. An external
resistor divider, R₁ and R₂, is used to set the output voltage as
shown in Equation 4. The recommended value for R₂ is 500Ω to
1kΩ. R₁ is then chosen according to Equation 5.
V_OUT
=
0.5
V
×
⎛
⎜
⎝
R_-----1-
R₂
+
⎞
1⎟
⎠
(EQ. 4)
R₁
=
R₂
×
⎛
⎝
V_{----O----U---T-}
0.5 V
–
1_⎠⎞
(EQ. 5)
Power Dissipation
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions” on page 5. The power
dissipation can be calculated by using Equation 6:
P_D = (V_IN – V_OUT) × I_OUT + V_IN × I_GND
(EQ. 6)
The maximum allowed junction temperature, T_J(MAX), and the
maximum expected ambient temperature, T_A(MAX), will
determine the maximum allowable power dissipation, as shown
in Equation 7:
P_D(MAX) = (T_J(MAX) – T_A) ⁄ θ_JA
(EQ. 7)
θ_JA is the junction-to-ambient thermal resistance.
For safe operation, ensure that the power disspiation P_D,
calculated from Equation 6, is less than the maximum allowable
power dissipation P_D(MAX).
Heatsinking the DFN Package
The DFN package uses the copper area on the PCB as a heat-sink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for heat sinking. Figure 17 shows a curve for the θ_JA of
the DFN package for different copper area sizes.
46
44
42
40
38
36
34
2 4 6 8 10 12 14 16 18 20 22 24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm²
FIGURE 17. 3mmx3mm 10 LD DFN ON 4-LAYER PCB WITH
THERMAL VIAS θ_JA vs EPAD-MOUNT COPPER LAND
AREA ON PCB
General PowerPAD Design
Considerations
Figure 18 shows the recommended use of vias on the thermal
pad to remove heat from the IC. This typical array populates the
thermal pad footprint with vias spaced three times the radius
distance from the center of each via. Small via size is advisable,
but not to the extent that solder reflow becomes difficult.
All vias should be connected to the pad potential, with low
thermal resistance for efficient heat transfer. Complete
connection of the plated-through hole to each plane is important.
It is not recommended to use “thermal relief” patterns to connect
the vias.
FIGURE 18. PCB VIA PATTERN
11
FN7810.0
February 17, 2011