ICE2AS01_06 Datasheet, PDF (11/24 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller

ICE2AS01/S01G
ICE2BS01/S01G
Functional Description
recovery time. To avoid a premature termination of the
switching pulse this spike is blanked out with a time
constant of t_LEB = 220ns. During that time the output of
the Current-Limit Comparator cannot switch off the
gate drive.
V_{OSC max. Duty Cycle}
3.5.2 Propagation Delay Compensation
In case of overcurrent detection the shut down of the
external Power Switch is delayed due to the
propagation delay of the circuit. This delay causes an
overshoot of the peak current I_peak which depends on
the ratio of dI/dt of the peak current (see Figure 14).
.
V_Sense
V_csth
off time
Propagation Delay t
I_Sense
I_peak2
I_peak1
I_Limit
Signal2
I_Overshoot2
Signal1
t_{Propagation Delay}
I_Overshoot1
Signal1
Signal2
t
Figure 15 Dynamic Voltage Threshold V_csth
t
Figure 14 Current Limiting
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform.
A propagation delay compensation is integrated to
bound the overshoot dependent on dI/dt of the rising
primary current. That means the propagation delay
time between exceeding the current sense threshold
V_csth and the switch off of the external Power Switch is
compensated over temperature within a range of at
least
.
0
≤
R_Sense
×
dI _peak
dt
≤ 1 ^dVSense
dt
So current limiting is now capable in a very accurate
way (see Figure 16).
E.g. I_peak = 0.5A with R_Sense = 2. Without propagation
delay compensation the current sense threshold is set
to a static voltage level V_csth=1V. A current ramp of
dI/dt = 0.4A/µs, that means dV_Sense/dt = 0.8V/µs, and a
propagation delay time of i.e. t_{Propagation Delay} =180ns
leads then to an I_peak overshoot of 14.4%. By means of
propagation delay compensation the overshoot is only
about 2% (see Figure 15).
The propagation delay compensation is done by
means of a dynamic threshold voltage V_csth (see Figure
15). In case of a steeper slope the switch off of the
driver is earlier to compensate the delay.
V
1,3
1,25
1,2
1,15
1,1
1,05
1
0,95
0,9
0
with compensation
without compensation
0,2 0,4 0,6 0,8
1 1,2 1,4 1,6 1,8
dV_Sense
dt
2_V
µs
Figure 16 Overcurrent Shutdown
3.6
PWM-Latch
The oscillator clock output applies a set pulse to the
PWM-Latch when initiating the external Power Switch
conduction. After setting the PWM-Latch can be reset
by the PWM-OP, the Soft-Start-Comparator, the
Current-Limit-Comparator, Comparator C3 or the
Error-Latch of the Protection Unit. In case of reseting
the driver is shut down immediately.
3.7
Driver
The driver is a fast totem pole gate drive, which is
designed to avoid cross conduction currents and which
is equipped with a Zener diode Z1 (see Figure 17) in
order to improve the control of the gate attached power
Datasheet
11
Preliminary Data
30 Jun 2006