PEB20571 Datasheet, PDF (109/308 Pages) Infineon Technologies AG – DSP Embedded Line and Port Interface Controller

PEB 20570
PEB 20571
Functional Description
Table 29 S/T Mode Multiframe Bit Positions
Frame number
1
LT-S to TE or
CO to LT-T,
F_a bit position
1
LT-S to TE or
CO to LT-T,
M-bit
1
LT-S to TE or
CO to LT-T,
S-bit
S11
2
0
0
S21
6
1
0
S12
7
0
0
S22
11
1
0
S13
12
0
0
S23
16
1
0
S14
17
0
0
S24
...
...
...
...
TE to LT-S or
LT-T to CO
F_a bit position
Q1
0
Q2
0
Q3
0
Q4
0
...
Note: 1.Only frame positions (within the 20-frame multiframe) that carry S- or Q-channel
information are shown here
2.The Q- and S-bits, which are not used, are set to ‘1’.
On the IOM-2000 interface, the S/T multiframe information is included in the DX/DR data
stream (transparent to the VIP). The values of the multiframe are controlled by the DSP
software in the DELIC.
When multiframe synchronization is not achieved or lost, the VIP mirrors the received F_a
bits. Once the multiframe synchronization is established, the DSP sends the multiframe
synchronization command to the VIP (MSYNC bit). Upon reception of the MSYNC, the
VIP stops mirroring the F_a -bit.
4.2.10.3 F_a/N Bit
In the transmit direction the F_a/N bit pair is coded in such a way that N is the binary
opposite of the F_a. The F_a bit is equal to binary ‘0’, except every 5^th frame when it is set
to ‘1’, which indicates the Q-bit position to the TE.
The receive direction, the F_a bit positions represent the Q-channel.
Data Sheet
92
2003-07-31