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XC886_1 Datasheet, PDF (108/144 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller
XC886/888CLM
Functional Description
However, it is important to note that the conversion error could increase due to loss of
charges on the capacitors, if fADC becomes too low during slow-down mode.
3.21.2 ADC Conversion Sequence
The analog-to-digital conversion procedure consists of the following phases:
• Synchronization phase (tSYN)
• Sample phase (tS)
• Conversion phase
• Write result phase (tWR)
conversion start
trigger
Sample Phase
fADCI
Source
interrupt
Conversion Phase
Channel Result
interrupt interrupt
BUSY Bit
SAMPLE Bit
tSYN
tS
tCONV
Write Result Phase
tWR
Figure 36 ADC Conversion Timing
Data Sheet
101
V0.9, 2006-12