TLE4263_07 Datasheet, PDF (10/19 Pages) Infineon Technologies AG – 5-V Low-Drop Voltage Regulator

TLE 4263
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
C_D which can be calculated as follows:
C_D = (t_rd × I_D,ch)/∆V
(1)
Definitions:
• C_D = delay capacitor
• t_rd = reset delay time
• I_D,ch = charge current, typical 60 µA
• ∆V = V_DU, typical 1.70 V
• V_DU = upper delay switching threshold at C_D for reset delay time
V_I
V_Q
V_{Q, rt}
V_D
V_DU
V_DRL
t_rd
t_rr
V_RO
< t_rr
t
dV
dt
=
I_{D, ch}
C_D
t
t
Power-ON
Over-
Voltage Drop Under- Secondary Load
Reset
temperature at Input voltage
Spike Bounce
t
AET03066
Figure 5 Time Response, Watchdog with High-Frequency Clock
Data Sheet
10
Rev. 2.8, 2007-03-20