TDA5100A Datasheet, PDF (10/29 Pages) Infineon Technologies AG – ASK Transmitter 434 MHz

TDA 5100A
preliminary
Functional Description
3.2 Pin Definitions and Functions
Table 3-2
Pin Symbol
No.
1
PDWN
Interface Schematic
V_S
4 0 µA ∗ D A T A
5 kΩ
1
150 kΩ
"O N "
250 kΩ
Function
Disable pin for the complete transmitter cir-
cuit.
A logic low (PDWN < 0.7 V) turns off all
transmitter functions.
A logic high (PDWN > 1.5 V) gives access to
all transmitter functions.
PDWN input will be pulled up by 40 µA inter-
nally by setting DATA to a logic high-state.
2
VS
3
GND
4
LF
V_S
140 pF
15 pF
35 kΩ
10 kΩ
4
This pin is the positive supply of the trans-
mitter electronics.
An RF bypass capacitor should be con-
nected directly to this pin and returned to
GND (pin 3) as short as possible.
General ground connection.
Output of the charge pump and input of the
VCO control voltage.
The loop bandwidth of the PLL is 150 kHz
when only the internal loop filter is used.
The loop bandwidth may be reduced by
applying an external RC network referencing
to the positive supply VS (pin 2).
Wireless Components
3-3
Specification, March 2001