ICE3DS01L Datasheet, PDF (10/27 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell

3.4
PWM Section
0.72
Oscillator
Duty Cycle
max
Clock
F3
ICE3DS01L/LG
Functional Description
PWM Section
PWM-Latch
1
VCC
Z1
Gate
Soft Start
Comparator
PWM
Comparator
FF1
1S
Gate Driver
G8
RQ
&
G9
Current
Limiting
Comparator
C3
Gate
Figure 7 PWM Section
Figure 8 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the external
Power Switch threshold. This is achieved by a slope
control of the rising edge at the driver’s output (see
Figure 9).
V_Gate
ca. t = 130ns
3.4.1
Oscillator
The oscillator generates a frequency f_switch = 110kHz. A
resistor, a capacitor and a current source and current
sink which determine the frequency are integrated. The
charging and discharging current of the implemented
oscillator capacitor are internally trimmed, in order to
achieve a very accurate switching frequency. The ratio
of controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D_max=0.72.
3.4.2
PWM-Latch FF1
The oscillator clock output provides a set pulse to the
PWM-Latch when initiating the external Power Switch
conduction. After setting the PWM-Latch can be reset
by the PWM comparator, the Soft Start comparator, the
Current-Limit comparator or comparator C3. In case of
resetting the driver is shut down immediately.
C_Load = 1nF
5V
t
Figure 9 Gate Rising Slope
Thus the leading switch on spike is minimized. When
the external Power Switch is switched off, the falling
shape of the driver is slowed down when reaching 2V
to prevent an overshoot below ground. Furthermore the
driver circuit is designed to eliminate cross conduction
of the output stage.
3.4.3
Gate Driver
The Gate Driver is a fast totem pole gate drive which is
designed to avoid cross conduction currents and which
is equipped with a zener diode Z1 (see Figure 8) in
order to improve the control of the Gate attached power
transistors as well as to protect them against
undesirable gate overvoltages.
The Gate Driver is active low at voltages below the
undervoltage lockout threshold V_VCCoff.
Version 2.0
10
15 May 2003