ICE2QR4765_10 Datasheet, PDF (10/21 Pages) Infineon Technologies AG – Off-Line SMPS Quasi-Resonant PWM Controller

CoolSET^® - Q1
ICE2QR4765
Functional Description
required maximum V_CS versus various input bus about Active Burst Mode operation are explained in the
voltage can be calculated, which is shown in Figure 6. following paragraphs.
1
0.9
0.8
0.7
0.6
80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400
Vin(V)
Figure 6 Variation of the VCS limit voltage according
to the IZC current
According to the typical application circuit, when
MOSFET is turned on, a negative voltage proportional
to bus voltage will be coupled to auxiliary winding.
Inside CoolSET^® -Q1, an internal circuit will clamp the
voltage on ZC pin to nearly 0V. As a result, the current
flowing out from ZC pin can be calculated as
IZC
=
-V----B-----U----S----N-----a-
RZC1NP
[5]
When this current is higher than I_{ZC_1}, the amount of
current exceeding this threshold is used to generate an
offset to decrease the maximum limit on V_CS. Since the
ideal curve shown in Figure 6 is a nonlinear one, a
digital block in CoolSET^® -Q1 is implemented to get a
better control of maximum output power. Additional
advantage to use digital circuit is the production
tolerance is smaller compared to analog solutions. The
typical maximum limit on V_CS versus the ZC current is
shown in Figure 7.
1
0.9
0.8
0.7
3.5.1
Entering Active Burst Mode Operation
For determination of entering Active Burst Mode
operation, three conditions apply:
• the feedback voltage is lower than the threshold of
V_FBEB(1.25V). Accordingly, the peak current sense
voltage across the shunt resistor is 0.17;
• the up/down counter is 7; and
• a certain blanking time (t_BEB).
Once all of these conditions are fulfilled, the Active
Burst Mode flip-flop is set and the controller enters
Active Burst Mode operation. This multi-condition
determination for entering Active Burst Mode operation
prevents mistriggering of entering Active Burst Mode
operation, so that the controller enters Active Burst
Mode operation only when the output power is really
low during the preset blanking time.
3.5.2
During Active Burst Mode Operation
After entering the Active Burst Mode the feedback
voltage rises as V_OUT starts to decrease due to the
inactive PWM section. One comparator observes the
feedback signal if the voltage level V_BH (3.6V) is
exceeded. In that case the internal circuit is again
activated by the internal bias to start with swtiching.
Turn-on of the power MOSFET is triggered by the
timer. The PWM generator for Active Burst Mode
operation composes of a timer with a fixed frequency of
52kHz, typically, and an analog comparator. Turn-off is
resulted by comparison of the voltage signal v₁ with an
internal threshold, by which the voltage across the
shunt resistor V_csB is 0.34V, accordingly. A turn-off can
also be triggered by the maximal duty ratio controller
which sets the maximal duty ratio to 50%. In operation,
the output flip-flop will be reset by one of these signals
which come first.
If the output load is still low, the feedback signal
decreases as the PWM section is operating. When
feedback signal reaches the low threshold V_BL(3.0V),
the internal bias is reset again and the PWM section is
disabled until next time regultaion siganl increases
beyond the V_BH threshold. If working in Active Burst
Mode the feedback signal is changing like a saw tooth
between 3.0V and 3.6V shown in Figure 8.
0.6
300
500
700
900 1100 1300 1500 1700 1900 2100
Iz c (uA)
Figure 7
V_CS-max versus I_ZC
3.5
Active Burst Mode Operation
At light load condition, the IC enters Active Burst Mode
operation to minimize the power consumption. Details
3.5.3
Leaving Active Burst Mode Operation
The feedback voltage immediately increases if there is
a high load jump. This is observed by one comparator.
As the current limit is 34% during Active Burst Mode a
certain load is needed so that feedback voltage can
exceed V_LB (4.5V). After leaving active busrt mode,
maximum current can now be provided to stabilize V_O.
In addition, the up/down counter will be set to 1
Version 2.1
10
February 5, 2010